ShEERA and UMUX layout and simulations

Layout for the ShERA row controller, diagonal switch-boxes, and part of a triangular switch-box in 90nm.

Transient response for an FPGA interconnection network. Note that the shape of the edge determines the switching energy consumption.

Good and bad edges for a pass-transistor MUX with level-restoring buffer.

Simulated 16-bit ShEERA Switch-box.

Simulated ShEERA system consisting of: (i) four triangular switch-boxes, (ii) three layers of carry-save adders, and (iii) a ripple carry adder.

Layout of Triangular Switch-box in 90nm.

Layout of UMUX vs Standard Level-Restoring Buffer in 350nm.

UMUX-LRB layout in 130nm.